1. Technical Field
This disclosure relates generally to pixel arrays, and in particular, but not exclusively to complementary metal-oxide semiconductor (“CMOS”) pixel arrays.
2. Background Art
FIG. 1 illustrates a pixel array structure, according to an existing technique, in which two neighboring CMOS image sensors (CIS) pixels 100 are formed within a p-type doped epitaxial (or “epi”) layer 140 disposed over a p-type doped silicon substrate 105. When a photo-generated charge carrier is formed shallow within pixel 100 (e.g., charge carrier 150), it experiences an attractive force (shown by the arrows 145) towards a photo-sensor or photodiode (“PD”) region 115, due to a depletion region or P-N junction between PD region 115 and the underlying p-type doped epi layer 140. In the illustrated embodiment, p-type doped pinning layers 135 overlay each of PD regions 115 to passivate their surfaces. CIS pixels 100 are separated by isolation structures—e.g. Shallow Trench Isolation (STI) regions 160—which are disposed within p-type doped wells 130. In each CIS pixel 100, additional pixel circuitry (not shown) is disposed adjacent to PD region 115 within a P doped well (not shown). Such pixel circuitry may commence acquisition of an image charge within PD region 115 to reset the image charge accumulated within PD region 115, to ready CIS pixel 100 for the next image, or to transfer out the image data acquired by CIS pixel 100.
When substrate 105 is made very thin, such as in the case of a Back Side Illuminated (BSI) CIS, and/or when the number of pixels is made very large, the lateral electrical resistance within substrate 105 may become relatively large and reduce performance of the pixel array. Performance limitations associated with increased substrate resistance are therefore problematic—particularly in BSI devices. For example, uniformity of dark is a common problem in image data generated with such devices. Other thin substrate devices such as those fabricated on Silicon On Insulator (SOI) substrates or those incorporating buried collector layers may also have similar problems. Today, such problems are addressed with the addition of ground contact structures within pixel substrate or p-well contacts—such as p+ doped contacts 180 within p-type doped wells 130—and with associated grounding metal layer traces coupled thereto.
For example, FIG. 2 shows elements of a typical pixel cell 200 for which grounding portion 218 provides ground contact 220 (e.g. contact 180) according to a conventional pixel array architecture. Pixel cell 200 includes photodiode PD 202, a transfer (Tx) transistor comprising Tx gate 204, a reset (RST) transistor comprising RST drain 208 and RST gate 210, and a source-follower (SF) transistor comprising SF source 212, SF gate 216 and SF drain 214. During operation of pixel cell 200, transfer gate 204 receives a transfer signal to transfer charge from PD 202 to floating diffusion node FD 206. RST drain 208 and RST gate 210 are operable to reset pixel cell 200 (e.g., to discharge or charge FD 206 and/or PD 202 to a preset voltage) under control of a reset signal provided to RST gate 210. FD 206 is coupled via a metal trace (not shown) to provide to SF gate 216 a potential for controlling a current exchange between SF source 212 and SF drain which, in turn, determines image data output from pixel cell 200.
Grounding portion 218 is formed in p-well and/or isolation structures adjoining PD 202 to reduce the effects of resistance in substrate 105. However, doping to form grounding portion 218 is a source of fabrication defects. For example, grounding portion 218 is often a minimum area determined by design rules. Mask alignment for such a small area is prone to overlap with doped regions of PD 202. Accordingly, P+ implantation to form grounding portion 218 tends to result in wounded pixels—e.g. where PD 202 has defects in its depletion area. Providing a larger area for grounding portion 218 tends to be at the cost of the available area for pixel cell 200—in particular, area for PD 202. For at least these reasons, conventional techniques for providing a ground contact structure for a pixel cell are limiting on photodiode performance.